//-----------------------------------------------------
// Design Name : Instruction Register v. 1.0.0
// File Name   : InstructionRegister.v 
// Function    : Your Ad Here
//-----------------------------------------------------
module InstructionRegister (
	clk,
	reset,
	enable,
	instruction, 
	opCode,
	rDest,
	iHigh,
	iLow
); 

// Input Ports 
input clk;
input reset;
input enable;
input [0:15] instruction;

// Output Ports 
output [3:0] opCode;
output [3:0] rDest;
output [3:0] iHigh;
output [3:0] iLow;

// Input Ports Data Type  
wire clk;
wire address;

// Output Ports Data Type 
reg [3:0] opCode;
reg [3:0] rDest;
reg [3:0] iHigh;
reg [3:0] iLow;

// Implementation
always @(posedge clk)
begin
	if(reset)
	begin
		opCode <= 4'd0;
		rDest  <= 4'd0;
		iHigh  <= 4'd0;
		iLow   <= 4'd0;
	end
	if(~reset & enable)
	begin
		opCode <= instruction[0:3];
		rDest  <= instruction[4:7];
		iHigh  <= instruction[8:11];
		iLow   <= instruction[12:15];
	end
end

endmodule 